5. Connection Example with FreeScale iMX21
S1R72V17 CPU Connection Guide EPSON 17
(Rev. 1.0)
• Bus cycle waveform
<Read cycle>
Bus c
cle Read access
HCL
bus clock
A
8:1
O
0
CS1
O
OE
O
<Write cycle>
Bus c
cle Write access
HCL
bus clock
A
8:1
O
0
CS1
O
RW
O
EB3
2
O
CSA
0HCLK
CSN (0HCLK)
OEA (2HCLK)
OEN (1HCLK)
WSC (8HCLK)
CSA
0HCLK
CSN (0HCLK)
RWA (2HCLK)
RWN (1HCLK)
WSC (8HCLK)
WEA (0HCLK)
WEN (0HCLK)
Fig. 5-3 iMX21 bus cycle waveform
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