Seiko Cal. V17 User Manual download pdf (Page 17)

4. CPUIF Verification Procedure

S1R72V17 CPU Connection Guide EPSON 13

(Rev. 1.0)

11) Internal clock feed confirmation

Read the MainIntStat register (0x000 address) to confirm that the FinishedPM bit (bit 0) has been set to

“1.”

If this bit is not set, it is likely that the clock is not fed from the external clock when the external clock

source is selected and that the oscillator is not oscillating correctly when the external oscillator is

selected.

In this case, the 0x008 address (MainIntEnb register) bit 0 (EnFinishedPM bit) should be set to “1.” This

asserts the XINT output pin to “Low.” Subsequently clearing the bit to “0” negates the XINT output pin

to “High.” This operation should be used to confirm that an interrupt occurs in the CPU.

Writing “1” to the MainIntStat register (0x000 address) bit 0 (FinishedPM bit) clears this status. Read

the MainIntStat register (0x000 address) bit 0 (FinishedPM bit) again to confirm that it has been cleared

to “0.”

12) Synchronous register access test (Word register)

Read/write test to/from the AREA0StartAdrs_L,H registers (0x080 address).

These registers can be read/written in the Active state.

The first 3 bits (bits [15:13]) and the last 2 bits (bits [1:0]) cannot be written to. They will always read

“0.”

13) Synchronous register access test (Byte register)

Read/write test to/from the D_EPaIntEnb register (0x0C6 address) and D_EPbIntEnb registers (0x0C7

address).

These registers can be read/written in the Active state.

The first bit (bit [7]) for the D_EPaIntEnb and D_EPbIntEnb registers cannot be written to and always

reads “0.”

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Seiko Cal. V17 User Manual Page 17