Seiko Cal. V17 User Manual download pdf (Page 11)

3. Endian Settings for 16-bit Bus Width Connection

S1R72V17 CPU Connection Guide EPSON 7

(Rev. 1.0)

3.2 Connection to Little-endian CPU

Access is normally in the mode with “1” set in the CPU_Config register (0x075h address)

CPU_Endian bit.

1) Access to Word register

The S1R72V17 connects the D[15:8] bus to the first byte of the Word register and the D[7:0]

bus to the last byte of the Word register.

The example below illustrates the writing and reading of 0x1234h data to/from the Word

Writing: The data (34h) in the CPU memory even-number address is saved to the last byte

of the S1R72V17 Word register.

Reading: The last byte data (34h) of the S1R72V17 Word register is saved to the

even-number address in CPU memory.

CPU

Data

・・・・

34h

Even-number address

12h

Odd-number address

Data in CPU memory

・・・・

Higher byte [15:8] Lower byte [7:0]

12h 34h CPU register

D[15:8] D[7:0] CPU data bus

D[15:0] bus connected unchanged

S1R72V17 D[15:8] D[7:0] V17 data bus

12h 34h V17 Word register

Higher byte [15:8] Lower byte [7:0]

_H, _HH, _LH registers _L, _HL, _LL registers

Fig. 3-4 Access to Word registers (little-endian CPU)

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 23 24

No comments

Seiko Cal. V17 User Manual Page 11