3. Endian Settings for 16-bit Bus Width Connection
8 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
2) Access to Byte register
The S1R72V17 connects the D[7:0] bus to the even-number address register and the D[15:8] bus
to the odd-number address register when the CPU_Endian bit is set to “1.”
The example below illustrates the writing and reading of F1h to/from the Byte register
even-number address register and of F2h to/from the Byte register odd-number address register.
Writing: The data (F1h) in the CPU memory even-number address is saved to the
S1R72V17 even-number address register.
Reading: The S1R72V17 even-number address register data (F1h) is saved to the
even-number address in CPU memory.
CPU
Data
・・・・
・・・・
F1h
Even-number address
F2h
Odd-number address
Data in CPU memory
・・・・
・・・・
Higher byte [15:8] Lower byte [7:0]
F2h F1h CPU register
D[15:8] D[7:0] CPU data bus
D[15:0] bus connected unchanged
S1R72V17 D[15:8] D[7:0] V17 data bus
F2h F1h V17 Byte register
Odd-number address Even-number address
re
ister register
Fig. 3-5 Access to Byte registers (little-endian CPU)
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